Driving method and device for shift register

ABSTRACT

A driving method and device for a shift register. In a data refreshing phase, loading an input signal having a pulse level to an input signal end, loading a control clock pulse signal to a control clock signal end, loading a noise reduction clock pulse signal to a noise reduction clock signal end, controlling a cascade signal end of the shift register to output a cascade signal having a pulse level, and controlling a drive signal end of the shift register to output a drive signal having a pulse level; in a data holding phase, loading a fixed voltage signal to the input signal end, loading a first set signal to the control clock signal end, loading a second set signal to the noise reduction clock signal end, controlling the cascade signal end to output a fixed voltage signal having a second level.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a national phase entry under 35 U.S.C §371 ofInternational Application No. PCT/CN2021/093329, filed May 12, 2021,which claims the priority to Chinese Patent Application No.202010552721.9, filed to the China National Intellectual PropertyAdministration on Jun. 17, 2020 and entitled “DRIVING METHOD AND DEVICEFOR SHIFT REGISTER”, which is incorporated in its entirety herein byreference.

FIELD

The present disclosure relates to the technical field of display, andparticularly relates to a driving method and device for a shiftregister.

BACKGROUND

Owing to rapid development of the display technology, display deviceshave been developing towards higher integration level and lower cost.The gate driver on array (GOA) technology integrates a thin filmtransistor (TFT) gate drive circuit on an array substrate of a displaydevice to form scanning drive for the display device. The gate drivecircuit is generally composed of a plurality of shift registers that arecascaded. However, high power consumption of a shift register will leadto high power consumption of a display device.

SUMMARY

Embodiments of the present disclosure provide a driving method for ashift register. The driving method includes: under a condition that atfirst refreshing frequency, a display frame includes a data refreshingphase and a data holding phase.

In the data refreshing phase, loading an input signal having a pulselevel to an input signal end, loading a control clock pulse signal to acontrol clock signal end, loading a noise reduction clock pulse signalto a noise reduction clock signal end, loading a fixed voltage signalhaving a first level to a first reference signal end, loading a fixedvoltage signal having a second level to a second reference signal end,controlling a cascade signal end of the shift register to output acascade signal having a pulse level, and controlling a drive signal endof the shift register to output a drive signal having a pulse level.

In the data holding phase, loading a fixed voltage signal to the inputsignal end, loading a first set signal to the control clock signal end,loading a second set signal to the noise reduction clock signal end,loading the fixed voltage signal having the first level to the firstreference signal end, loading the fixed voltage signal having the secondlevel to the second reference signal end, controlling the cascade signalend to output the fixed voltage signal having the second level, andcontrolling the drive signal end to output the fixed voltage signalhaving the first level.

The control clock pulse signal has the first level, the second level anda first clock period, the first set signal has a first set level, wherethe first clock period includes a duration of one first level and aduration of one second level of the control clock pulse signal, one ofthe first level and the second level of the control clock pulse signalis a control clock pulse level, the control clock pulse level is thesame as the first set level, and a maintaining duration of the first setlevel in the first clock period is longer than a maintaining duration ofthe control clock pulse level in the first clock period.

And/or, the noise reduction clock pulse signal has a first level, asecond level and a second clock period, the second set signal has asecond set level, where the second clock period includes a duration ofone first level and a duration of one second level of the noisereduction clock pulse signal, one of the first level and the secondlevel of the noise reduction clock pulse signal is a noise reductionclock pulse level, the noise reduction clock pulse level is the same asthe second set level, and a maintaining duration of the second set levelin the second clock period is longer than a maintaining duration of thenoise reduction clock pulse level in the second clock period.

In some examples, the first set signal is a clock pulse signal, and thefirst set level is one of the first level and the second level.

In some examples, a third clock period of the first set signal is longerthan the first clock period, and the third clock period includes aduration of one first level and a duration of one second level of thefirst set signal.

In some examples, a maintaining duration of the first level of the firstset signal in the first clock period is longer than a maintainingduration of the first level of the control clock pulse signal in thefirst clock period; and a maintaining duration of the second level ofthe first set signal in the first clock period is longer than amaintaining duration of the second level of the control clock pulsesignal in the first clock period.

In some examples, the second set signal is a clock pulse signal, and thesecond set level is one of the first level and the second level.

In some examples, a fourth clock period of the second set signal islonger than the second clock period, and the fourth clock periodincludes a duration of one first level and a duration of one secondlevel of the second set signal.

In some examples, a maintaining duration of the first level of thesecond set signal in the second clock period is longer than amaintaining duration of the first level of the noise reduction clockpulse signal in the second clock period; and a maintaining duration ofthe second level of the second set signal in the second clock period islonger than a maintaining duration of the second level of the noisereduction clock pulse signal in the second clock period.

In some examples, a third clock period of the first set signal is thesame as the fourth clock period of the second set signal.

In some examples, at least one of the first set signal and the secondset signal is a fixed voltage signal; and at least one of the first setlevel and the second set level is one of the first level and the secondlevel.

In some examples, the first level is a high level, and the second levelis a low level; or, the first level is a low level, and the second levelis a high level.

In some examples, the driving method further includes: under a conditionthat at second refreshing frequency, a display frame includes a datarefreshing phase, in the data refreshing phase, loading the input signalhaving the pulse level to the input signal end, loading the controlclock pulse signal to the control clock signal end, loading the noisereduction clock pulse signal to the noise reduction clock signal end,loading the fixed voltage signal having the first level to the firstreference signal end, loading the fixed voltage signal having the secondlevel to the second reference signal end, controlling the cascade signalend of the shift register to output the cascade signal having the pulselevel, and controlling the drive signal end of the shift register tooutput the drive signal having the pulse level.

The embodiments of the present disclosure provide a driving circuit fora shift register. At first refreshing frequency, a display frameincludes a data refreshing phase and a data holding phase; and thedriving circuit is configured to:

-   -   in the data refreshing phase, load an input signal having a        pulse level to an input signal end, load a control clock pulse        signal to a control clock signal end, load a noise reduction        clock pulse signal to a noise reduction clock signal end, load a        fixed voltage signal having a first level to a first reference        signal end, load a fixed voltage signal having a second level to        a second reference signal end, control a cascade signal end of        the shift register to output a cascade signal having a pulse        level, and control a drive signal end of the shift register to        output a drive signal having a pulse level; and    -   in the data holding phase, load a fixed voltage signal to the        input signal end, load a first set signal to the control clock        signal end, load a second set signal to the noise reduction        clock signal end, load the fixed voltage signal having the first        level to the first reference signal end, load the fixed voltage        signal having the second level to the second reference signal        end, control the cascade signal end to output the fixed voltage        signal having the second level, and control the drive signal end        to output the fixed voltage signal having the first level.

The control clock pulse signal has the first level, the second level anda first clock period, the first set signal has a first set level, wherethe first clock period includes a duration of one first level and aduration of one second level of the control clock pulse signal, one ofthe first level and the second level of the control clock pulse signalis a control clock pulse level, the control clock pulse level is thesame as the first set level, and a maintaining duration of the first setlevel in the first clock period is longer than a maintaining duration ofthe control clock pulse level in the first clock period.

And/or, the noise reduction clock pulse signal has the first level, asecond level and a second clock period, the second set signal has asecond set level, where the second clock period includes a duration ofone first level and a duration of one second level of the noisereduction clock pulse signal, one of the first level and the secondlevel of the noise reduction clock pulse signal is a noise reductionclock pulse level, the noise reduction clock pulse level is the same asthe second set level, and a maintaining duration of the second set levelin the second clock period is longer than a maintaining duration of thenoise reduction clock pulse level in the second clock period.

In some examples, at second refreshing frequency, a display frameincludes the data refreshing phase; and the driving circuit is furtherconfigured to:

-   -   in the data refreshing phase, load the input signal having the        pulse level to the input signal end, load the control clock        pulse signal to the control clock signal end, load the noise        reduction clock pulse signal to the noise reduction clock signal        end, load the fixed voltage signal having the first level to the        first reference signal end, load the fixed voltage signal having        the second level to the second reference signal end, control the        cascade signal end of the shift register to output the cascade        signal having the pulse level, and control the drive signal end        of the shift register to output the drive signal having the        pulse level.

The embodiments of the present disclosure provide a display panel. Thedisplay panel includes a gate drive circuit and the driving circuitdescribed above, where the gate drive circuit includes a plurality ofshift registers that are cascaded; and the driving circuit iselectrically connected to the plurality of shift registers.

The embodiments of the present disclosure provide a display device. Thedisplay device includes a display panel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic structural diagram of a shift register provided inan embodiment of the present disclosure.

FIG. 2 is a flowchart of a driving method provided in an embodiment ofthe present disclosure.

FIG. 3 shows some signal sequence diagrams provided in an embodiment ofthe present disclosure.

FIG. 4 shows some analogue simulation diagrams provided in an embodimentof the present disclosure.

FIG. 5 shows some other signal sequence diagrams provided in anembodiment of the present disclosure.

FIG. 6 shows still some signal sequence diagrams provided in anembodiment of the present disclosure.

FIG. 7 shows still some signal sequence diagrams provided in anembodiment of the present disclosure.

FIG. 8 shows some other analogue simulation diagrams provided in anembodiment of the present disclosure.

FIG. 9 is a schematic structural diagram of some gate drive circuitsprovided in an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

To make the objectives, technical solutions, and advantages inembodiments of the present disclosure clearer, the technical solutionsin the embodiments of the present disclosure will be clearly andcompletely described below with reference to the accompanying drawingsin the embodiments of the present disclosure. It is obvious that thedescribed embodiments are some rather than all of the embodiments of thepresent disclosure. Moreover, the embodiments of the present disclosureand features in the embodiments can be combined with one another withoutconflict. Based on the described embodiments of the present disclosure,all other embodiments obtained by those of ordinary skill in the artwithout inventive efforts fall within the scope of protection of thepresent disclosure.

Unless otherwise defined, technical terms or scientific terms used inthe present disclosure should have ordinary meanings understood by thoseof ordinary skill in the art to which the present disclosure belongs.Words “first”, “second” etc. used in the present disclosure do notdenote any order, quantity, or importance, but are merely used fordistinguishing between different components. Words “comprising”,“encompassing”, etc., are intended to mean that an element or item infront of the word encompasses elements or items that are listed behindthe word and equivalents thereof, but do not exclude other elements oritems. Words “connection”, “connected”, etc. are not limited to aphysical or mechanical connection, but can include an electricalconnection, whether direct or indirect.

It should be noted that dimensions and shapes of all graphs in theaccompanying drawings do not reflect true ratios, and are merelyintended to illustrate contents of the present disclosure. Moreover, thesame or similar reference numerals denote the same or similar elementsor elements having the same or similar function throughout.

Generally, in order to reduce power consumption of a display device, thedisplay device may be driven at lower refreshing frequency (such as 1Hz). Due to long-term leakage accumulation of a transistor, a signaloutput from a drive signal end is abnormal.

The embodiments of the present disclosure provide some shift registers.As shown in FIG. 1 , the shift register may include the followingelements.

A first transistor M1, where a gate electrode of the first transistor M1is coupled to a first reference signal end VREF1, a first electrode ofthe first transistor M1 is coupled to a first pull-up node PU_1, and asecond electrode of the first transistor M1 is coupled to a secondpull-up node PU_2.

A second transistor M2, where a gate electrode of the second transistorM2 is coupled to a cascade signal end GP, a first electrode of thesecond transistor M2 is coupled to a second reference signal end VREF2,and a second electrode of the second transistor M2 is coupled to a gateelectrode of a fifth transistor M5.

A third transistor M3, where a gate electrode of the third transistor M3is coupled to a first noise reduction clock signal end CKO, a firstelectrode of the third transistor M3 is coupled to the first referencesignal end VREF1, and a second electrode of the third transistor M3 iscoupled to the gate electrode of the fifth transistor M5.

A fourth transistor M4, where a gate electrode of the fourth transistorM4 is coupled to the cascade signal end GP, a first electrode of thefourth transistor M4 is coupled to the second reference signal endVREF2, and a second electrode of the fourth transistor M4 is coupled toa drive signal end OP.

The fifth transistor M5, where a first electrode of the fifth transistorM5 is coupled to the first reference signal end VREF1, and a secondelectrode of the fifth transistor M5 is coupled to the drive signal endOP.

A first capacitor C1, where a first electrode of the first capacitor C1is coupled to a second noise reduction clock signal end CKBO, and asecond electrode of the first capacitor C1 is coupled to the gateelectrode of the fifth transistor M5.

A second capacitor C2, where a first electrode of the second capacitorC2 is coupled to the gate electrode of the fifth transistor M5, and asecond electrode of the second capacitor C2 is coupled to the drivesignal end OP.

A sixth transistor M6, where a gate electrode of the sixth transistor M6is coupled to the second pull-up node PU_2, a first electrode of thesixth transistor M6 is coupled to a second control clock signal end CKB,and a second electrode of the sixth transistor M6 is coupled to thecascade signal end GP.

A seventh transistor M7, where a gate electrode of the seventhtransistor M7 is coupled to a pull-down node PD, a first electrode ofthe seventh transistor M7 is coupled to the second reference signal endVREF2, and a second electrode of the seventh transistor M7 is coupled tothe cascade signal end GP.

A third capacitor C3, where a first electrode of the third capacitor C3is coupled to the second pull-up node PU_2, and a second electrode ofthe third capacitor C3 is coupled to the cascade signal end GP.

A fourth capacitor C4, where a first electrode of the fourth capacitorC4 is coupled to the pull-down node PD, and a second electrode of thefourth capacitor C4 is coupled to the second reference signal end VREF2.

An eighth transistor M8, where a gate electrode of the eighth transistorM8 is coupled to a first control clock signal end CK, a first electrodeof the eighth transistor M8 is coupled to an input signal end IP, and asecond electrode of the eighth transistor M8 is coupled to the firstpull-up node PU_1.

A ninth transistor M9, where a gate electrode of the ninth transistor M9is coupled to the first control clock signal end CK, a first electrodeof the ninth transistor M9 is coupled to the first reference signal endVREF1, and a second electrode of the ninth transistor M9 is coupled tothe pull-down node PD.

A tenth transistor M10, where a gate electrode of the tenth transistorM10 is coupled to the first pull-up node PU_1, a first electrode of thetenth transistor M10 is coupled to the first control clock signal endCK, and a second electrode of the tenth transistor M10 is coupled to thepull-down node PD.

An eleventh transistor M11, where a gate electrode of the eleventhtransistor M11 is coupled to the pull-down node PD, a first electrode ofthe eleventh transistor M11 is coupled to the second reference signalend VREF2, and a second electrode of the eleventh transistor M11 iscoupled to a first electrode of a twelfth transistor M12.

The twelfth transistor M12, where a gate electrode of the twelfthtransistor M12 is coupled to the second control clock signal end CKB,and a second electrode of the twelfth transistor M12 is coupled to thefirst pull-up node PU_1.

During specific implementation, as shown in FIG. 1 , the first pull-upnode PU_1 is coupled between the second electrode of the eighthtransistor M8 and the first electrode of the first transistor M1. Thesecond pull-up node PU_2 is coupled between the gate electrode of thesixth transistor M6 and the second electrode of the first transistor M1.The pull-down node PD is coupled between the second electrode of theninth transistor M9 and the gate electrode of the seventh transistor M7.It should be noted that the first pull-up node PU_1, the second pull-upnode PU_2 and the pull-down node PD are virtual nodes in the shiftregister. The three nodes are merely for convenience of describing astructure of the shift register and signal transmission, and a specificstructure of the shift register and signal transmission may bedetermined according to a coupling mode between each transistor and thecapacitor in the shift register.

According to the shift register provided in the embodiment of thepresent disclosure, a corresponding signal is loaded to each signal end,such that each transistor and the capacitor work together in acooperative manner, and a cascade signal end and a drive signal end mayoutput corresponding signals separately. In addition, power consumptionof the shift register may be further reduced, such that the shiftregister in the present application may be advantageously used in adisplay device having lower refreshing frequency.

During specific implementation, according to a flow direction of asignal, for each of the transistors, the first electrode may be used asa source electrode and the second electrode may be used as a drainelectrode; and alternatively, the first electrode may be used as a drainelectrode and the second electrode may be used as a source electrode,which are not specifically distinguished herein.

It should be noted that each of the transistors mentioned in theembodiments of the present disclosure may be a thin film transistor(TFT) or a metal oxide semiconductor (MOS) field effect transistor,which is not limited herein.

To reduce a manufacturing process, during specific implementation, inthe embodiments of the present disclosure, each transistor may be aP-type transistor, as shown in FIG. 1 . The P-type transistor is turnedon when a voltage difference V_(gs) between a gate electrode and asource electrode of the P-type transistor and a threshold voltage V_(th)satisfy V_(gs)<V_(th). For example, when the third transistor M3 is aP-type transistor, the third transistor M3 is turned on when a voltagedifference V_(gs3) between a gate electrode and a source electrodethereof and a threshold voltage V_(th3) satisfy V_(gs3)<V_(th3).Certainly, the embodiments of the present disclosure merely takes thetransistors as the P-type transistors as an example for illustration.When the transistors are N-type transistors, a design principle thereforis the same as that of the present disclosure, and also belongs to thescope of protection of the present disclosure. In addition, each N-typetransistor is turned on when a voltage difference V_(gs) between a gateelectrode and a source electrode thereof and a threshold voltage V_(th)satisfy V_(gs)>V_(th). For example, when the third transistor M3 is anN-type transistor, the third transistor M3 is turned on when a voltagedifference V_(gs3) between a gate electrode and a source electrodethereof and a threshold voltage V_(th3) satisfy V_(gs3)>V_(th3).

Furthermore, during specific implementation, the P-type transistor isturned off under an effect of a high-level signal and turned on under aneffect of a low-level signal. The N-type transistor is turned on underan effect of a high-level signal and turned off under an effect of alow-level signal.

During specific implementation, a width-to-length ratio of a channelregion of an active layer of at least one of the fourth transistor M4,the fifth transistor M5, the sixth transistor M6 and the seventhtransistor M7 may be greater than that of a channel region of an activelayer of at least one of the first transistor M1, the second transistorM2, the third transistor M3, the eighth transistor M8, the ninthtransistor M9, the tenth transistor M10, the eleventh transistor M11 andthe twelfth transistor M12. For example, a width-to-length ratio of achannel region of an active layer of the fourth transistor M4, awidth-to-length ratio of a channel region of an active layer of thefifth transistor M5, a width-to-length ratio of a channel region of anactive layer of the sixth transistor M6 and a width-to-length ratio of achannel region of an active layer of the seventh transistor M7 may begreater than a width-to-length ratio of a channel region of an activelayer of the first transistor M1, a width-to-length ratio of a channelregion of an active layer of the second transistor M2, a width-to-lengthratio of a channel region of an active layer of the third transistor M3,a width-to-length ratio of a channel region of an active layer of theeighth transistor M8, a width-to-length ratio of a channel region of anactive layer of the ninth transistor M9, a width-to-length ratio of achannel region of an active layer of the tenth transistor M10, awidth-to-length ratio of a channel region of an active layer of theeleventh transistor M11 and a width-to-length ratio of a channel regionof an active layer of the twelfth transistor M12.

During specific implementation, the width-to-length ratio of the channelregion of the active layer of the at least one of the fourth transistorM4, the fifth transistor M5, the sixth transistor M6 and the seventhtransistor M7 may range from 10 μm/2 μm to 100 μm/10 μm. For example,each of the width-to-length ratio of the channel region of the activelayer of the fourth transistor M4, the width-to-length ratio of thechannel region of the active layer of the fifth transistor M5, thewidth-to-length ratio of the channel region of the active layer of thesixth transistor M6 and the width-to-length ratio of the channel regionof the active layer of the seventh transistor M7 may range from 10 μm/2μm to 100 μm/10 μm. For example, each of the width-to-length ratio ofthe channel region of the active layer of the fourth transistor M4, thewidth-to-length ratio of the channel region of the active layer of thefifth transistor M5, the width-to-length ratio of the channel region ofthe active layer of the sixth transistor M6 and the width-to-lengthratio of the channel region of the active layer of the seventhtransistor M7 may be 10 μm/2 μm. Also, each of the width-to-length ratioof the channel region of the active layer of the fourth transistor M4,the width-to-length ratio of the channel region of the active layer ofthe fifth transistor M5, the width-to-length ratio of the channel regionof the active layer of the sixth transistor M6 and the width-to-lengthratio of the channel region of the active layer of the seventhtransistor M7 may be 100 μm/10 μm. Also, each of the width-to-lengthratio of the channel region of the active layer of the fourth transistorM4, the width-to-length ratio of the channel region of the active layerof the fifth transistor M5, the width-to-length ratio of the channelregion of the active layer of the sixth transistor M6 and thewidth-to-length ratio of the channel region of the active layer of theseventh transistor M7 may be 50 μm/5 μm.

Certainly, in actual use, the width-to-length ratio of the channelregion of the active layer of the fourth transistor M4, thewidth-to-length ratio of the channel region of the active layer of thefifth transistor M5, the width-to-length ratio of the channel region ofthe active layer of the sixth transistor M6 and the width-to-lengthratio of the channel region of the active layer of the seventhtransistor M7 may be specifically designed according to requirements ofthe actual use, which are not limited herein.

During specific implementation, the width-to-length ratio of the channelregion of the active layer of the at least one of the first transistorM1, the second transistor M2, the third transistor M3, the eighthtransistor M8, the ninth transistor M9, the tenth transistor M10, theeleventh transistor M11 and the twelfth transistor M12 may be 2 μm/2 μmto 20 μm/10 μm. For example, the width-to-length ratio of the channelregion of the active layer of the first transistor M1, thewidth-to-length ratio of the channel region of the active layer of thesecond transistor M2, the width-to-length ratio of the channel region ofthe active layer of the third transistor M3, the width-to-length ratioof the channel region of the active layer of the eighth transistor M8,the width-to-length ratio of the channel region of the active layer ofthe ninth transistor M9, the width-to-length ratio of the channel regionof the active layer of the tenth transistor M10, the width-to-lengthratio of the channel region of the active layer of the eleventhtransistor M11 and the width-to-length ratio of the channel region ofthe active layer of the twelfth transistor M12 may range from 2 μm/2 μmto 20 μm/10 μm. For example, the width-to-length ratio of the channelregion of the active layer of the first transistor M1, thewidth-to-length ratio of the channel region of the active layer of thesecond transistor M2, the width-to-length ratio of the channel region ofthe active layer of the third transistor M3, the width-to-length ratioof the channel region of the active layer of the eighth transistor M8,the width-to-length ratio of the channel region of the active layer ofthe ninth transistor M9, the width-to-length ratio of the channel regionof the active layer of the tenth transistor M10, the width-to-lengthratio of the channel region of the active layer of the eleventhtransistor M11 and the width-to-length ratio of the channel region ofthe active layer of the twelfth transistor M12 may be 2 μm/2 μm. Also,the width-to-length ratio of the channel region of the active layer ofthe first transistor M1, the width-to-length ratio of the channel regionof the active layer of the second transistor M2, the width-to-lengthratio of the channel region of the active layer of the third transistorM3, the width-to-length ratio of the channel region of the active layerof the eighth transistor M8, the width-to-length ratio of the channelregion of the active layer of the ninth transistor M9, thewidth-to-length ratio of the channel region of the active layer of thetenth transistor M10, the width-to-length ratio of the channel region ofthe active layer of the eleventh transistor M11 and the width-to-lengthratio of the channel region of the active layer of the twelfthtransistor M12 may be 20 μm/10 μm. Also, the width-to-length ratio ofthe channel region of the active layer of the first transistor M1, thewidth-to-length ratio of the channel region of the active layer of thesecond transistor M2, the width-to-length ratio of the channel region ofthe active layer of the third transistor M3, the width-to-length ratioof the channel region of the active layer of the eighth transistor M8,the width-to-length ratio of the channel region of the active layer ofthe ninth transistor M9, the width-to-length ratio of the channel regionof the active layer of the tenth transistor M10, the width-to-lengthratio of the channel region of the active layer of the eleventhtransistor M11 and the width-to-length ratio of the channel region ofthe active layer of the twelfth transistor M12 may be 10 μm/5 μm.

Certainly, in actual use, the width-to-length ratio of the channelregion of the active layer of the first transistor M1, thewidth-to-length ratio of the channel region of the active layer of thesecond transistor M2, the width-to-length ratio of the channel region ofthe active layer of the third transistor M3, the width-to-length ratioof the channel region of the active layer of the eighth transistor M8,the width-to-length ratio of the channel region of the active layer ofthe ninth transistor M9, the width-to-length ratio of the channel regionof the active layer of the tenth transistor M10, the width-to-lengthratio of the channel region of the active layer of the eleventhtransistor M11 and the width-to-length ratio of the channel region ofthe active layer of the twelfth transistor M12 may be specificallydesigned according to actual use requirements, which are not limitedherein.

During specific implementation, a capacitance of at least one of thefirst capacitor C1, the second capacitor C2, the third capacitor C3 andthe fourth capacitor C4 may ranges from 10 fF to 1 pF. For example, thecapacitance of the at least one of the first capacitor C1, the secondcapacitor C2, the third capacitor C3 and the fourth capacitor C4 may be10 fF. Also, the capacitance of the at least one of the first capacitorC1, the second capacitor C2, the third capacitor C3 and the fourthcapacitor C4 may be 50 fF. Also, the capacitance of the at least one ofthe first capacitor C1, the second capacitor C2, the third capacitor C3and the fourth capacitor C4 may be 1 pF. Certainly, in actual use, acapacitance of the first capacitor C1, a capacitance of the secondcapacitor C2, a capacitance of the third capacitor C3 and a capacitanceof the fourth capacitor C4 may be specifically designed according torequirements of the actual use, which are not limited herein.

What is described above is just an example to illustrate a specificstructure of the shift register provided in the embodiment of thepresent disclosure. During specific implementation, specific structuresof the above circuits are not limited to the above structures providedin the embodiment of the present disclosure, but can also be otherstructures known to those skilled in the art, which are not limitedherein.

The embodiments of the present disclosure further provide a drivingmethod for a shift register. As shown in FIGS. 2 and 3 , at firstrefreshing frequency, a display frame includes a data refreshing phaseT10 and a data holding phase T20.

The driving method may include the following steps.

S210, in the data refreshing phase, loading an input signal having apulse level to an input signal end, loading a control clock pulse signalto a control clock signal end, loading a noise reduction clock pulsesignal to a noise reduction clock signal end, loading a fixed voltagesignal having a first level to a first reference signal end, loading afixed voltage signal having a second level to a second reference signalend, controlling a cascade signal end of the shift register to output acascade signal having a pulse level, and controlling a drive signal endof the shift register to output a drive signal having a pulse level.

S220, in the data holding phase, loading a fixed voltage signal to theinput signal end, loading a first set signal to the control clock signalend, loading a second set signal to the noise reduction clock signalend, loading the fixed voltage signal having the first level to thefirst reference signal end, loading the fixed voltage signal having thesecond level to the second reference signal end, controlling the cascadesignal end to output the fixed voltage signal having the second level,and controlling the drive signal end to output the fixed voltage signalhaving the first level.

According to the driving method for a shift register provided in theembodiments of the present disclosure, in the data refreshing phase T10,the input signal having the pulse level is loaded to the input signalend, the control clock pulse signal is loaded to the control clocksignal end, the noise reduction clock pulse signal is loaded to thenoise reduction clock signal end, the fixed voltage signal having thefirst level is loaded to the first reference signal end, the fixedvoltage signal having the second level is loaded to the second referencesignal end, the cascade signal end of the shift register is controlledto output the cascade signal having the pulse level, and the drivesignal end of the shift register is controlled to output the drivesignal having the pulse level. In this way, cascade output and driveoutput of the shift register may be implemented, such that the displaydevice may refresh data.

In addition, in the data holding phase, the fixed voltage signal isloaded to the input signal end, the first set signal is loaded to thecontrol clock signal end, the second set signal is loaded to the noisereduction clock signal end, the fixed voltage signal having the firstlevel is loaded to the first reference signal end, the fixed voltagesignal having the second level is loaded to the second reference signalend, the cascade signal end is controlled to output the fixed voltagesignal having the second level, and the drive signal end is controlledto output the fixed voltage signal having the first level.

For example, the control clock pulse signal is a clock pulse signalhaving the first level and the second level that are alternatelyswitched. In addition, the control clock pulse signal has a first clockperiod, and the first level and the second level are switched in thefirst clock period. The first clock period includes a duration of onefirst level and a duration of one second level of the control clockpulse signal. One of the first level and the second level of the controlclock pulse signal may be a control clock pulse level, and the first setsignal has a first set level. The control clock pulse level is the sameas the first set level, and a maintaining duration of the first setlevel in the first clock period is longer than a maintaining duration ofthe control clock pulse level in the first clock period. In this way,frequency of level switching of the first set signal in the data holdingphase may be reduced, such that power consumption may be decreased.

For example, the noise reduction clock pulse signal is a clock pulsesignal having the first level and the second level that are alternatelyswitched. In addition, the noise reduction clock pulse signal has asecond clock period, and the first level and the second level areswitched in the second clock period. The second clock period includes aduration of one first level and a duration of one second level of thenoise reduction clock pulse signal. One of the first level and thesecond level of the noise reduction clock pulse signal may be a noisereduction clock pulse level, and the second set signal has a second setlevel. The noise reduction clock pulse level is the same as the secondset level, and a maintaining duration of the second set level in thesecond clock period is longer than a maintaining duration of the noisereduction clock pulse level in the second clock period. In this way,frequency of level switching of the second set signal in the dataholding phase may be reduced, such that power consumption may bedecreased.

Generally, the display device may be in a static image display state orstandby state for a long time. In order to reduce power consumption, thedisplay device may be operated at lower refreshing frequency (such as 1Hz or 30 Hz). According to the shift register in the embodiments of thepresent disclosure, the first set signal and the second set signal areloaded in the data holding phase, such that power consumption may bereduced, and then the shift register in the present application may beadvantageously used in a display device having lower refreshingfrequency.

During specific implementation, in the embodiments of the presentdisclosure, the first level may a low level, and the second level may bea high level. Alternatively, the first level may also be a high level,and the second level may also be a low level. In actual use, design anddetermination may be conducted according to actual use requirements,which is not limited herein.

During specific implementation, in the embodiments of the presentdisclosure, the driving method further includes the following steps thatunder a condition that at second refreshing frequency, a display frameincludes a data refreshing phase T10, in the data refreshing phase,loading the input signal having the pulse level to the input signal end,loading the control clock pulse signal to the control clock signal end,loading the noise reduction clock pulse signal to the noise reductionclock signal end, loading the fixed voltage signal having the firstlevel to the first reference signal end, loading the fixed voltagesignal having the second level to the second reference signal end,controlling the cascade signal end of the shift register to output thecascade signal having the pulse level, and controlling the drive signalend of the shift register to output the drive signal having the pulselevel.

Generally, the display device may be in a static image display state orstandby state for a long time. In order to reduce power consumption, thedisplay device may be operated at lower refreshing frequency (such as 1Hz or 30 Hz). Certainly, the display device may also display videoimages. In order to improve a display effect of the video images, thedisplay device may be operated at higher refreshing frequency (such as60 Hz or 120 Hz). During specific implementation, in the embodiments ofthe present disclosure, the first refreshing frequency may be lowerrefreshing frequency, such as 1 Hz or 30 Hz. The second refreshingfrequency may be higher refreshing frequency, such as 60 Hz or 120 Hz.

During specific implementation, in the embodiments of the presentdisclosure, the control clock signal end includes the first controlclock signal end CK and the second control clock signal end CKB; and thecontrol clock pulse signal includes a first control clock pulse signaland a second control clock pulse signal. Each of periods of the firstcontrol clock pulse signal and the second control clock pulse signal isthe first clock period, and a phase difference between the period of thefirst noise reduction clock pulse signal and the period of the secondnoise reduction clock pulse signal is ½ period. In addition, in the datarefreshing phase T10, the control clock pulse signal is loaded to thecontrol clock signal end, which may specifically include the followingsteps that the first control clock pulse signal is loaded to the firstcontrol clock signal end CK, and the second control clock pulse signalis loaded to the second control clock signal end CKB.

For example, as shown in FIGS. 1 and 3 , ck represents a signal loadedby the first control clock signal end CK, and ckb represents a signalloaded by the second control clock signal end CKB. In the datarefreshing phase T10, the first control clock pulse signal loaded by thefirst control clock signal end CK is a clock pulse signal having a highlevel and a low level that are switched, and the second control clockpulse signal loaded by the second control clock signal end CKB is also aclock pulse signal having the high level and the low level that areswitched. In addition, the first control clock pulse signal and thesecond control clock pulse signal have the same period and a phasedifference of a ½ period. For example, a duty cycle of the first controlclock pulse signal is the same as a duty cycle of the second controlclock pulse signal, and the duty cycle is greater than 50%. Certainly,in actual use, specific implementation modes of the first control clockpulse signal and the second control clock pulse signal may be designedand determined according to actual use requirements, which are notlimited herein.

During specific implementation, in the embodiments of the presentdisclosure, in the data holding phase, the fixed voltage signal isloaded to the input signal end IP, which may include the following stepthat the fixed voltage signal having the second level is loaded to theinput signal end IP. For example, as shown in FIGS. 1 and 3 , iprepresents a signal loaded by the input signal end IP. When a transistorin the shift register is a P-type transistor, the fixed voltage signalhaving the high level may be loaded to the input signal end IP. When atransistor in the shift register is an N-type transistor, the fixedvoltage signal having the low level may be loaded to the input signalend IP.

During specific implementation, in the embodiments of the presentdisclosure, in the data holding phase, the cascade signal end GP iscontrolled to output a fixed voltage signal, and the drive signal end OPis controlled to output a fixed voltage signal, which may include thefollowing steps that the cascade signal end GP is controlled to outputthe fixed voltage signal having the second level, and the drive signalend OP is controlled to output the fixed voltage signal having the firstlevel. For example, as shown in FIGS. 1 and 3 , gp represents a signaloutput from the cascade signal end GP, and op represents a signal outputfrom the drive signal end OP. When a transistor in the shift register isa P-type transistor, the cascade signal end GP may be controlled tooutput the fixed voltage signal having a high level, and the drivesignal end OP may be controlled to output the fixed voltage signalhaving a low level. When a transistor in the shift register is an N-typetransistor, the cascade signal end GP may be controlled to output thefixed voltage signal having a low level, and the drive signal end OP maybe controlled to output the fixed voltage signal having a high level.

During specific implementation, in the embodiments of the presentdisclosure, the pulse level of the input signal may be the first level.In this way, when the eighth transistor M8 is turned on, the pulse levelof the input signal may be input to the first pull-up node PU_1, suchthat a level of the first pull-up node PU_1 is the first level, and thetenth transistor M10 may be controlled to be turned on by the level ofthe first pull-up node PU_1. For example, as shown in FIGS. 1 and 3 ,when a transistor in the shift register is a P-type transistor, thepulse level of the input signal is a low level. When a transistor in theshift register is an N-type transistor, the pulse level of the inputsignal is a high level.

During specific implementation, in the embodiments of the presentdisclosure, the pulse level of the cascade signal may be the firstlevel. In this way, the fourth transistor M4 may be controlled to beturned on by the pulse level of the cascade signal, and a signal of thesecond reference signal end VREF2 is supplied to the drive signal endOP. For example, as shown in FIGS. 1 and 3 , when a transistor in theshift register is a P-type transistor, the pulse level of the cascadesignal is a low level. When a transistor in the shift register is anN-type transistor, the pulse level of the cascade signal is a highlevel.

During specific implementation, in the embodiments of the presentdisclosure, the fixed voltage signal of the first reference signal endVREF1 may have the first level, the fixed voltage signal of the secondreference signal end VREF2 may have the second level, and the pulselevel of the drive signal may have the second level. For example, asshown in FIGS. 1 and 3 , when a transistor in the shift register is aP-type transistor, the first level is a low level and the second levelis a high level. When a transistor in the shift register is an N-typetransistor, the first level is a high level and the second level is alow level.

During specific implementation, in the embodiments of the presentdisclosure, the noise reduction clock signal end may include the firstnoise reduction clock signal end CKO and the second noise reductionclock signal end CKBO. The noise reduction clock pulse signal includes afirst noise reduction clock pulse signal and a second noise reductionclock pulse signal. Each of periods of the first noise reduction clockpulse signal and the second noise reduction clock pulse signal is thesecond clock period, and a phase difference between the period of thefirst noise reduction clock pulse signal and the period of the secondnoise reduction clock pulse signal is ½ period. In addition, in the datarefreshing phase T10, the noise reduction clock pulse signal is loadedto the noise reduction clock signal end, which may include the followingsteps that the first noise reduction clock pulse signal is loaded to thefirst noise reduction clock signal end CKO, and the second noisereduction clock pulse signal is loaded to the second noise reductionclock signal end CKBO.

For example, as shown in FIGS. 1 and 3 , cko represents a signal loadedby the first noise reduction clock signal end CKO, and ckbo represents asignal loaded by the second noise reduction clock signal end CKBO. Inthe data refreshing phase T10, the first noise reduction clock pulsesignal loaded by the first noise reduction clock signal end CKO is aclock pulse signal having a high level and a low level that areswitched, and the second noise reduction clock pulse signal loaded bythe second noise reduction clock signal end CKBO is also a clock pulsesignal having a high level and a low level that are switched. Inaddition, the first noise reduction clock pulse signal and the secondnoise reduction clock pulse signal have the same period and a phasedifference of a ½ period. For example, a duty cycle of the first noisereduction clock pulse signal is the same as a duty cycle of the secondnoise reduction clock pulse signal, and the duty cycle is greater than50%. Certainly, in actual use, specific implementation modes of thefirst noise reduction clock pulse signal and the second noise reductionclock pulse signal may be designed and determined according to actualuse requirements, which are not limited herein.

In some examples, as shown in FIG. 3 , the first clock period of thefirst noise reduction clock pulse signal may be the same as the secondclock period of the first control clock pulse signal, that is, the firstclock period may be the same as the second clock period. Furthermore,the duty cycle of the first noise reduction clock pulse signal may bethe same as the duty cycle of the first control clock pulse signal. Forexample, a falling edge of the first noise reduction clock pulse signalis aligned with a rising edge of a second control clock pulse signal. Afalling edge of the second noise reduction clock pulse signal is alignedwith a rising edge of the first control clock pulse signal. Certainly,in actual use, relations between the first noise reduction clock pulsesignal, the second noise reduction clock pulse signal, the first controlclock pulse signal and the second control clock pulse signal may bedesigned and determined according to actual requirements, which are notlimited herein.

During specific implementation, in the embodiments of the presentdisclosure, in the data holding phase, the first set signal is loaded tothe control clock signal end, and the first set signal has the first setlevel. The control clock pulse level is the same as the first set level,and the maintaining duration of the first set level in the first clockperiod is longer than the maintaining duration of the control clockpulse level in the first clock period. For example, as shown in FIGS. 1and 3 , ck represents a signal loaded by the first control clock signalend CK, and ckb represents a signal loaded by the second control clocksignal end CKB. In the data holding phase T20, the first set signal ofthe fixed voltage signal is loaded to the first control clock signal endCK. For example, when the first set level is the first level, a controlclock pulse level of the first control clock pulse signal loaded by thefirst control clock signal end CK and a control clock pulse level of thesecond control clock pulse signal loaded by the second control clocksignal end CKB are also first levels. With the first level as a lowlevel as an example, as shown in FIG. 3 , when the first set signal iskept to have a low level in the data holding phase, that is, the signalloaded by the first control clock signal end CK is kept to have a lowlevel in the data holding phase, and the signal loaded by the secondcontrol clock signal end CKB is kept to have a low level in the dataholding phase, the maintaining duration of the first set level in thefirst clock period may be longer than the maintaining duration of thecontrol clock pulse level in the first clock period, such that powerconsumption of the shift register may be reduced.

For example, when the first set level is the second level, the controlclock pulse level is also the second level. With the second level as ahigh level as an example, as shown in FIG. 6 , when the first set signalis kept to have a high level in the data holding phase, the maintainingduration of the first set level in the first clock period may be longerthan the maintaining duration of the control clock pulse level in thefirst clock period, such that power consumption of the shift registermay be reduced.

During specific implementation, in the embodiments of the presentdisclosure, in the data holding phase, the second set signal is loadedto the noise reduction clock signal end, and the second set signal hasthe second set level. The noise reduction clock pulse level is the sameas the second set level, and the maintaining duration of the second setlevel in the second clock period is longer than the maintaining durationof the noise reduction clock pulse level in the second clock period. Forexample, as shown in FIGS. 1 and 3 , the second set signal may be afixed voltage signal. For example, when the second set level is thefirst level, the noise reduction clock pulse level is also the firstlevel. With the first level as a low level as an example, as shown inFIG. 3 , when the second set signal is kept to have a low level in thedata holding phase, that is, the signal loaded by the first noisereduction clock signal end CKO is kept to have a low level in the dataholding phase, and the signal loaded by the second noise reduction clocksignal end CKBO is kept to have a low level in the data holding phase,such that power consumption of the shift register may be reduced.

For example, when the second set level is the second level, the noisereduction clock pulse level is also the second level. With the secondlevel as a high level as an example, as shown in FIG. 6 , when thesecond set signal is kept to have a high level in the data holdingphase, the maintaining duration of the second set level in the secondclock period may be longer than the maintaining duration of the noisereduction clock pulse level in the second clock period, such that powerconsumption of the shift register may be reduced.

With the shift register shown in FIG. 1 as an example below, bycombining a signal sequence diagram shown in FIG. 3 , a work process ofthe shift register provided in the embodiments of the present disclosureat the first refreshing frequency will be described. In the followingdescription, 1 represents a high level and 0 represents a low level. Itshould be noted that 1 and 0 represent logic levels, which are merelyfor better illustration of a specific work process of the embodiment ofthe present disclosure, rather than a voltage applied to a gateelectrode of each transistor during specific implementation.

Specifically, as shown in FIG. 3 , at the first refreshing frequency, adisplay frame may include the data refreshing phase T10 and the dataholding phase T20. It should be noted that the signal sequence diagramshown in FIG. 3 merely shows a work process of a shift register in acurrent display frame. Work processes of the shift register in otherdisplay frames are basically the same as the work process of the shiftregister in the current display frame, which will not be repeatedherein.

The data refreshing phase T10 includes phases T11, T12, T13 and T14.Specifically, in T11, ip=0, ckb=1, ck=0, cko=0, ckbo=1. When ckb=1, thetwelfth transistor M12 is turned off. When ck=0, the ninth transistor M9is turned on, and a low-level signal of the first reference signal endVREF1 is supplied to the pull-down node PD, such that a signal of thepull-down node PD is a low-level signal, and then the seventh transistorM7 is controlled to be turned on. The turned-on seventh transistor M7supplies a high-level signal of the second reference signal end VREF2 tothe cascade signal end GP, such that the cascade signal end GP outputs ahigh-level signal. When ck=0, the eighth transistor M8 is turned on, anda low-level signal of the input signal end IP is supplied to the firstpull-up node PU_1, such that a signal of the first pull-up node PU_1 isa low-level signal. Then, the tenth transistor M10 is controlled to beturned on, such that a low-level signal of the first control clocksignal end CK is supplied to the pull-down node PD, and then a signal ofthe pull-down node PD is a low-level signal. When the first transistorM1 satisfies V_(gs1)<V_(th1), the first transistor M1 is turned on. Theturned-on first transistor M1 turns on the second pull-up node PU_2 andthe first pull-up node PU_1, such that a signal of the second pull-upnode PU_2 may be a low-level signal in time, and the sixth transistor M6is controlled to be turned on; and a high-level signal of the secondcontrol clock signal end CKB is supplied to the cascade signal end GP,such that the cascade signal end GP outputs a high-level cascade signal.When the cascade signal end GP outputs a high-level signal, the secondtransistor M2 and the fourth transistor M4 may be controlled to beturned off When cko=0, the third transistor M3 is turned on, and thelow-level signal of the first reference signal end VREF1 is supplied tothe gate electrode of the fifth transistor M5. Then, the fifthtransistor M5 is controlled to be turned on, such that the low-levelsignal of the first reference signal end VREF1 is supplied to the drivesignal end OP, and then the drive signal end OP outputs a low-leveldrive signal.

In T12, ip=1, ckb=0, ck=1, cko=1, ckbo=0. When ck=1, the ninthtransistor M9 and the eighth transistor M8 are turned off. Under aneffect of the third capacitor C3, the second pull-up node PU_2 is keptto have a low-level signal, the sixth transistor M6 is controlled to beturned on, and then a low-level signal of the second control clocksignal end CKB is supplied to the cascade signal end GP, such that thecascade signal end GP outputs a low-level cascade signal. Under aneffect of the third capacitor C3, a level of the second pull-up nodePU_2 is lowered, and the sixth transistor M6 is controlled to be turnedon as thoroughly as possible. Then, the low-level signal of the secondcontrol clock signal end CKB is supplied to the cascade signal end GP,such that the cascade signal end GP outputs the low-level cascadesignal. In addition, in the phase, an electrode of the first transistorM1 coupled to the first pull-up node PU_1 is used as the sourceelectrode thereof, such that the first transistor M1 cannot satisfyV_(gs1)<V_(th1), the first transistor M1 may be turned off, then thelevel of the second pull-up node PU_2 may be kept stable, and unstableoutput of the cascade signal end GP due to rise of the level of thesecond pull-up node PU_2 caused by electric leakage may be avoided.

In addition, the tenth transistor M10 supplies a high-level signal ofthe first control clock signal end CK to the pull-down node PD undercontrol of the signal of the first pull-up node PU_1, and the seventhtransistor M7 is controlled to be turned off, such that an adverseinfluence on the signal output from the cascade signal end GP isavoided. When cko=1, the third transistor M3 is turned off. When thecascade signal end GP outputs a low-level signal, the second transistorM2 and the fourth transistor M4 may be controlled to be turned on. Theturned-on second transistor M2 may supply the high-level signal of thesecond reference signal end VREF2 to the gate electrode of the fifthtransistor M5, and the fifth transistor M5 is controlled to be turnedoff. The turned-on fourth transistor M4 may supply the high-level signalof the second reference signal end VREF2 to the drive signal end OP,such that the drive signal end OP outputs a high-level drive signal.

After T12 and before T13, when ckb=1, the twelfth transistor M12 isturned off When ck=1, the ninth transistor M9 and the eighth transistorM8 are turned off. Under an effect of the third capacitor C3, the secondpull-up node PU_2 is kept to have the low-level signal, the sixthtransistor M6 is controlled to be turned on, and then the high-levelsignal of the second control clock signal end CKB is supplied to thecascade signal end GP, such that the cascade signal end GP outputs ahigh-level cascade signal, and the second transistor M2 and the fourthtransistor M4 are controlled to be turned off. When the signal cko ofthe first noise reduction clock signal end CKO is converted from thehigh level to the low level, the third transistor M3 is turned on, thelow-level signal of the first reference signal end VREF1 is supplied tothe gate electrode of the fifth transistor M5. Then, the fifthtransistor M5 is controlled to be turned on, such that the low-levelsignal of the first reference signal end VREF1 is supplied to the drivesignal end OP, and then the drive signal end OP outputs the low-leveldrive signal.

In T13, ip=1, ckb=1, ck=0, cko=0, ckbo=1.

When ckb=1, the twelfth transistor M12 is turned off. When ck=0, theeighth transistor M8 and the ninth transistor M9 are turned on. Theturned-on eighth transistor M8 supplies a high-level signal of the inputsignal end IP to the first pull-up node PU_1, such that the firstpull-up node PU_1 has a high-level signal, and the tenth transistor M10is controlled to be turned off. When the first reference signal endVREF1 has the low-level signal, the first transistor M1 is turned on,the high-level signal of the first pull-up node PU_1 is supplied to thesecond pull-up node PU_2, and then the sixth transistor M6 is controlledto be turned off. The turned-on ninth transistor M9 supplies thelow-level signal of the first reference signal end VREF1 to thepull-down node PD, such that the signal of the pull-down node PD is thelow-level signal, and then the seventh transistor M7 is controlled to beturned on. The turned-on seventh transistor M7 supplies the high-levelsignal of the second reference signal end VREF2 to the cascade signalend GP, such that the cascade signal end GP outputs the high-levelsignal, and the second transistor M2 and the fourth transistor M4 arecontrolled to be turned off When cko=0, the third transistor M3 isturned on, and the low-level signal of the first reference signal endVREF1 may be supplied to the gate electrode of the fifth transistor M5.Then, the fifth transistor M5 is controlled to be turned on, such thatthe low-level signal of the first reference signal end VREF1 is suppliedto the drive signal end OP, and then the drive signal end OP outputs thelow-level drive signal. In addition, the first capacitor C1 and thesecond capacitor C2 keep a voltage difference between two ends thereofstable.

In T14, ip=1, ckb=0, ck=1, cko=1, ckbo=0.

When ck=1, the eighth transistor M8 and the ninth transistor M9 areturned off. Under an effect of the fourth capacitor C4, the pull-downnode PD may be kept to have the low-level signal, the seventh transistorM7 is controlled to be turned on, and then the high-level signal of thesecond reference signal end VREF2 is supplied to the cascade signal endGP, such that the cascade signal end GP outputs the high-level signal,and the second transistor M2 and the fourth transistor M4 are controlledto be turned off When cko=0, the third transistor M3 is turned on, andthe low-level signal of the first reference signal end VREF1 may besupplied to the gate electrode of the fifth transistor M5. Then, thefifth transistor M5 is controlled to be turned on, such that thelow-level signal of the first reference signal end VREF1 is supplied tothe drive signal end OP, and then the drive signal end OP outputs thelow-level drive signal. In addition, the eleventh transistor M11 and thetwelfth transistor M12 are turned on, such that the first pull-up nodePU_1 has the high-level signal, then the second pull-up node PU_2 hasthe high-level signal, and the sixth transistor M6 is controlled to beturned off.

After T14, work processes of T13 and T14 are repeatedly executed until adenoising and holding phase T21-1 is entered.

In the data holding phase T20, ip=1, ckb=0, ck=0, cko=0, ckbo=0. Whenck=0, the eighth transistor M8 and the ninth transistor M9 are turnedon. The turned-on eighth transistor M8 inputs the high-level signal ofthe input signal end IP into the first pull-up node PU_1, such that thefirst pull-up node PU_1 has the high-level signal, and the sixthtransistor M6 is controlled to be turned off. The turned-on ninthtransistor M9 supplies the low-level signal of the first referencesignal end VREF1 to the pull-down node PD, such that the signal of thepull-down node PD is the low-level signal, and then the seventhtransistor M7 is controlled to be turned on. The turned-on seventhtransistor M7 supplies the high-level signal of the second referencesignal end VREF2 to the cascade signal end GP, such that the cascadesignal end GP outputs the high-level signal. When the cascade signal endGP outputs the high-level signal, the second transistor M2 and thefourth transistor M4 may be controlled to be turned off When cko=0, thethird transistor M3 is turned on, and the low-level signal of the firstreference signal end VREF1 is supplied to the gate electrode of thefifth transistor M5. Then, the fifth transistor M5 is controlled to beturned on, such that the low-level signal of the first reference signalend VREF1 is supplied to the drive signal end OP, and then the drivesignal end OP outputs the low-level drive signal.

It should be noted that in actual use, specific voltages of all thesignals mentioned above may be designed and determined according to anactual use environment, which are not limited herein.

Furthermore, according to the signal sequence diagram shown in FIG. 3 ,analogue simulation is conducted on a signal output from the drivesignal end OP of the shift register shown in FIG. 1 , and an analoguesimulation diagram is shown in FIG. 4 . In FIG. 4 , an abscissarepresents time, an ordinate represents voltage, and S1 represents asignal subjected to analogue simulation on the drive signal end OP ofthe shift register shown in FIG. 1 according to the signal sequencediagram shown in FIG. 3 . With reference to FIGS. 3 and 4 , in theembodiments of the present disclosure, the first set signal and thesecond set signal in the data holding phase are set, such that the drivesignal end OP may output a signal stably.

In addition, the shift register shown in FIG. 1 is further driven towork according to the signal sequence diagram shown in FIG. 3 , andpower consumption of the shift register is detected to be 0.4 mW duringwork in the data holding phase T20. Therefore, power consumption of theshift register may also be within an acceptable range.

With the shift register shown in FIG. 1 as an example below, bycombining the signal sequence diagram shown in FIG. 5 , a work processof the shift register provided in the embodiments of the presentdisclosure at the second refreshing frequency will be described. In thefollowing description, 1 represents a high-level signal and 0 representsa low-level signal. It should be noted that 1 and 0 represent logiclevels, which are merely for better illustration of a specific workprocess of the embodiments of the present disclosure, rather than avoltage applied to a gate electrode of each transistor during specificimplementation.

Specifically, as shown in FIG. 5 , at the second refreshing frequency, adisplay frame may include the data refreshing phase T10. It should benoted that the signal sequence diagram shown in FIG. 5 merely shows awork process of a shift register in a current display frame. Workprocesses of the shift register in other display frames are basicallythe same as the work process of the shift register in the currentdisplay frame, which will not be repeated herein.

The data refreshing phase T10 includes phases T11, T12, T13 and T14. Inaddition, a work process of the shift register provided in theembodiments of the present disclosure in the signal sequence diagramshown in FIG. 5 is basically the same as a work process of the shiftregister in the data refreshing phase T10 in the signal sequence diagramshown in FIG. 3 , which will not be repeated herein.

With the shift register shown in FIG. 1 as an example below, bycombining a signal sequence diagram shown in FIG. 6 , a work process ofthe shift register provided in the embodiments of the present disclosureat the first refreshing frequency will be described.

Specifically, as shown in FIG. 6 , at the first refreshing frequency, adisplay frame may include the data refreshing phase T10 and the dataholding phase T20. It should be noted that the signal sequence diagramshown in FIG. 6 merely shows a work process of a shift register in acurrent display frame. Work processes of the shift register in otherdisplay frames are basically the same as the work process of the shiftregister in the current display frame, which will not be repeatedherein.

The data refreshing phase T10 includes phases T11, T12, T13 and T14. Inaddition, a work process of the shift register provided in theembodiments of the present disclosure in the signal sequence diagramshown in FIG. 6 is basically the same as a work process of the shiftregister in the data refreshing phase T10 in the signal sequence diagramshown in FIG. 3 , which will not be repeated herein.

In the data holding phase T20, ip=1, ckb=1, ck=1, cko=1, ckbo=1. Whenck=1, the eighth transistor M8 and the ninth transistor M9 are turnedoff. Under an effect of the third capacitor C3, the second pull-up nodePU_2 is kept to have the high-level signal, and the sixth transistor M6is controlled to be turned off. Under an effect of the fourth capacitorC4, the pull-down node PD is kept to have the low-level signal, and theseventh transistor M7 is controlled to be turned on. The turned-onseventh transistor M7 supplies the high-level signal of the secondreference signal end VREF2 to the cascade signal end GP, such that thecascade signal end GP outputs the high-level signal. When the cascadesignal end GP outputs the high-level signal, the second transistor M2and the fourth transistor M4 may be controlled to be turned off. Whencko=1, the third transistor M3 is turned off. Under an effect of thesecond capacitor C2, the fifth transistor M5 may be controlled to beturned on, such that the low-level signal of the first reference signalend VREF1 is supplied to the drive signal end OP, and then the drivesignal end OP outputs the low-level drive signal.

The embodiments of the present disclosure further provide some otherdriving methods, which are varied with respect to the implementationmodes in the embodiments mentioned above. Herein, merely differencesbetween the embodiment and the embodiments mentioned above will bedescribed, and the same part will not be repeated herein.

During specific implementation, in the embodiment of the presentdisclosure, as shown in FIG. 7 , when the first set signal is the clockpulse signal, the first set level may be one of the first level and thesecond level, that is, the first set signal may also be the clock pulsesignal having the high level and the low level that are switched. Thefirst set signal has a third clock period t03, the third clock periodt03 includes a duration of one first level and a duration of one secondlevel of the first set signal, and the third clock period t03 may belonger than the first clock period tOl.

For example, the first set level is the first level. A maintainingduration of the first level of the first set signal in the first clockperiod is longer than a maintaining duration of the first level of thecontrol clock pulse signal in the first clock period. For example, asshown in FIG. 7 , with the first level as the high level as an example,a maintaining duration of a high level in a period of the first setsignal in the first clock period t01 is longer than a maintainingduration of a high level in a period of the control clock pulse signalin the first clock period t01. Furthermore, a maintaining duration of ahigh level in a period of the first set signal in the third clock periodt03 is longer than the maintaining duration of the high level in theperiod of the control clock pulse signal in the first clock period t01.

For example, the first set level is the second level. A maintainingduration of the second level of the first set signal in the first clockperiod is longer than a maintaining duration of the second level of thecontrol clock pulse signal in the first clock period. For example, asshown in FIG. 7 , with the second level as the low level as an example,a maintaining duration of a low level in a period of the first setsignal in the first clock period t01 is longer than a maintainingduration of a low level in a period of the control clock pulse signal inthe first clock period t01. Furthermore, a maintaining duration of a lowlevel in a period of the first set signal in the third clock period t03is longer than the maintaining duration of the low level in the periodof the control clock pulse signal in the first clock period t01.

During specific implementation, in the embodiments of the presentdisclosure, as shown in FIG. 7 , when the second set signal is the clockpulse signal, the second set level may be one of the first level and thesecond level, that is, the second set signal may also be the clock pulsesignal having the high level and the low level that are switched. Thesecond set signal has a fourth clock period t04, the fourth clock periodt04 includes a duration of one first level and a duration of one secondlevel of the second set signal, and the fourth clock period t04 may belonger than the second clock period t02.

For example, the second set level is the first level. A maintainingduration of the first level of the second set signal in the second clockperiod is longer than a maintaining duration of the first level of thenoise reduction clock pulse signal in the second clock period. Forexample, as shown in FIG. 7 , with the first level as the high level asan example, a maintaining duration of a high level in a period of thesecond set signal in the second clock period t02 is longer than amaintaining duration of a high level in a period of the noise reductionclock pulse signal in the second clock period t02. Furthermore, amaintaining duration of a high level in a period of the second setsignal in the fourth clock period t04 is longer than the maintainingduration of the high level in the period of the noise reduction clockpulse signal in the second clock period t02.

For example, the second set level is the second level. A maintainingduration of the second level of the second set signal in the secondclock period is longer than a maintaining duration of the second levelof the noise reduction clock pulse signal in the second clock period.For example, as shown in FIG. 7 , with the second level as the low levelas an example, a maintaining duration of a low level in a period of thesecond set signal in the second clock period t02 is longer than amaintaining duration of a low level in a period of the noise reductionclock pulse signal in the second clock period t02. Furthermore, amaintaining duration of a low level in a period of the second set signalin the fourth clock period t04 is longer than the maintaining durationof the low level in the period of the noise reduction clock pulse signalin the second clock period t02.

For example, the third clock period t03 of the first set signal may bethe same as the fourth clock period t04 of the second set signal, suchthat coupling interference of signals may be reduced.

With the shift register shown in FIG. 1 as an example below, bycombining a signal sequence diagram shown in FIG. 7 , a work process ofthe shift register provided in the embodiments of the present disclosureat the first refreshing frequency will be described. In the followingdescription, 1 represents a high-level signal and 0 represents alow-level signal. It should be noted that 1 and 0 represent logiclevels, which are merely for better illustration of a specific workprocess of the embodiment of the present disclosure, rather than avoltage applied to a gate electrode of each transistor during specificimplementation.

Specifically, as shown in FIG. 7 , at the first refreshing frequency, adisplay frame may include the data refreshing phase T10 and the dataholding phase T20. It should be noted that the signal sequence diagramshown in FIG. 7 merely shows a work process of a shift register in acurrent display frame. Work processes of the shift register in otherdisplay frames are basically the same as the work process of the shiftregister in the current display frame, which will not be repeatedherein.

A work process in the data refreshing phase T10 may refer to the workprocess mentioned above, which will not be repeated herein.

A work process in the data holding phase T20 is basically the same asthat after T14 in the data refreshing phase T10. The difference is thatfrequency of switching between the high level and the low level ofsignal ckb, signal ck, signal cko and signal ckbo in the data holdingphase T20 is lower than that in the data refreshing phase T10, so aspecific work process will not be repeated herein.

Furthermore, according to the signal sequence diagram shown in FIG. 7 ,analogue simulation is conducted on a signal output from the drivesignal end OP of the shift register shown in FIG. 1 , and an analoguesimulation diagram is shown in FIG. 8 . In FIG. 8 , an abscissarepresents time, an ordinate represents voltage, and S2 represents asignal subjected to analogue simulation on the drive signal end OP ofthe shift register shown in FIG. 1 according to the signal sequencediagram shown in FIG. 7 . With reference to FIGS. 7 and 8 , in theembodiments of the present disclosure, the first set signal and thesecond set signal in the data holding phase are set, such that the drivesignal end OP may output a signal stably.

In addition, the shift register shown in FIG. 1 is further driven towork according to the signal sequence diagram shown in FIG. 7 , andpower consumption of the shift register is detected to be 0.7 mW duringwork in the data holding phase T20. Therefore, even if a clock pulse isinserted in the data holding phase T20, power consumption of the shiftregister may also be within an acceptable range.

The embodiments of the present disclosure further provide a gate drivecircuit. As shown in FIG. 9 , the gate drive circuit includes any of aplurality of above cascaded shift registers provided in the embodimentsof the present disclosure: SR(1), SR(2) . . . SR(n−1), SR(n). . .SR(N−1), SR(N) (N shift registers in total, 1≤n≤N, and n is an integer).An input signal end IP of a first shift register SR(1) is configured tobe coupled to a frame trigger signal end (STV).

In every two adjacent shift registers, an input signal end IP of a nextshift register SR(n) is configured to be coupled to a cascade signaloutput end GP of a previous shift register SR(n−1).

Specifically, a specific structure and functions of each of the shiftregisters in the gate drive circuit mentioned above are the same asthose of the shift register of the present disclosure, which will not berepeated herein. The gate drive circuit may be configured in a liquidcrystal display panel or an electroluminescent display panel, which isnot limited herein.

Specifically, in the gate drive circuit provided in the embodiments ofthe present disclosure, a first reference signal end VREF1 of each ofthe shift registers is coupled to a same first direct current signalend, and a second reference signal end VREF2 of each of the shiftregisters is coupled to a same second direct current signal end.

Specifically, in the gate drive circuit provided in the embodiments ofthe present disclosure, first control clock signal ends CK ofodd-numbered shift registers and second control clock signal ends CKB ofeven-numbered shift registers are coupled to the same clock end, whichis a first control clock end. Second control clock signal ends CKB ofthe odd-numbered shift registers and first control clock signal ends CKof the even-numbered shift registers are coupled to the same clock end,which is a second control clock end.

Specifically, in the gate drive circuit provided in the embodiments ofthe present disclosure, first noise reduction clock signal ends CKO ofodd-numbered shift registers and second noise reduction clock signalends CKBO of even-numbered shift registers are coupled to the same clockend, which is a first noise reduction clock end. Second noise reductionclock signal ends CKBO of the odd-numbered shift registers and firstnoise reduction clock signal ends CKO of the even-numbered shiftregisters are coupled to the same clock end, which is a second noisereduction clock end.

Based on the same disclosed concept, the embodiments of the presentdisclosure further provide a driving circuit for a shift register. Atfirst refreshing frequency, a display frame includes a data refreshingphase and a data holding phase.

The driving circuit is configured to: in the data refreshing phase, loadan input signal having a pulse level to an input signal end, load acontrol clock pulse signal to a control clock signal end, load a noisereduction clock pulse signal to a noise reduction clock signal end, loada fixed voltage signal having a first level to a first reference signalend, load a fixed voltage signal having a second level to a secondreference signal end, control a cascade signal end of the shift registerto output a cascade signal having a pulse level, and control a drivesignal end of the shift register to output a drive signal having a pulselevel; and

-   -   in the data holding phase, load a fixed voltage signal to the        input signal end, load a first set signal to the control clock        signal end, load a second set signal to the noise reduction        clock signal end, load the fixed voltage signal having the first        level to the first reference signal end, load the fixed voltage        signal having the second level to the second reference signal        end, control the cascade signal end to output the fixed voltage        signal having the second level, and control the drive signal end        to output the fixed voltage signal having the first level.

The control clock pulse signal has the first level, the second level anda first clock period, the first set signal has a first set level, wherethe first clock period includes a duration of one first level and aduration of one second level of the control clock pulse signal, one ofthe first level and the second level of the control clock pulse signalis a control clock pulse level, the control clock pulse level is thesame as the first set level, and a maintaining duration of the first setlevel in the first clock period is longer than that of the control clockpulse level in the first clock period; and/or, the noise reduction clockpulse signal has the first level, the second level and a second clockperiod, the second set signal has a second set level, where the secondclock period includes a duration of one first level and a duration ofone second level of the noise reduction clock pulse signal, one of thefirst level and the second level of the noise reduction clock pulsesignal is a noise reduction clock pulse level, the noise reduction clockpulse level is the same as the second set level, and a maintainingduration of the second set level in the second clock period is longerthan a maintaining duration of the noise reduction clock pulse level inthe second clock period.

During specific implementation, in the embodiments of the presentdisclosure, at second refreshing frequency, a display frame includes thedata refreshing phase. The driving circuit is further configured to: inthe data refreshing phase, load the input signal having the pulse levelto the input signal end, load the control clock pulse signal to thecontrol clock signal end, load the noise reduction clock pulse signal tothe noise reduction clock signal end, load the fixed voltage signalhaving the first level to the first reference signal end, load the fixedvoltage signal having the second level to the second reference signalend, control the cascade signal end of the shift register to output thecascade signal having the pulse level, and control the drive signal endof the shift register to output the drive signal having the pulse level.

It should be noted that a work process of the driving circuit may referto a process of the driving method mentioned above, which will not berepeated herein.

Based on the same disclosed concept, the embodiments of the presentdisclosure further provide a display panel. The display panel includesthe gate drive circuit provided in the embodiments of the presentdisclosure and the driving circuit mentioned above. The driving circuitis electrically connected to a plurality of shift registers.

A problem solution principle of the display panel is similar to that ofthe driving circuit mentioned above, so implementation of the displaypanel may refer to implementation of the driving circuit mentionedabove, which will not be repeated herein.

Based on the same disclosed concept, the embodiments of the presentdisclosure further provide a display device. The display device includesthe display panel provided in the embodiments of the present disclosure.A problem solution principle of the display device is similar to that ofthe display panel mentioned above, so implementation of the displaydevice may refer to implementation of the display panel mentioned above,which will not be repeated herein.

During specific implementation, the display device provided in theembodiments of the present disclosure may be a mobile phone, a tablet, atelevision, a display apparatus, a laptop, a digital photo frame, anavigator and other products or components having display functions.

Other essential components of the display device will be understood bythose of ordinary skill in the art, and will not be repeated herein, norare they intended to be limiting of the present disclosure.

Although preferred embodiments of the present disclosure are described,those of ordinary skill in the art can make additional changes andmodifications to the embodiments once they learn the basic inventiveconcept. Therefore, the appended claims are intended to be interpretedas including the preferred embodiments and all changes and modificationsfalling within the scope of the present disclosure.

Apparently, those of ordinary skill in the art can make variousmodifications and variations to the embodiments of the presentdisclosure without departing from the spirit and scope of theembodiments of the present disclosure. In this way, if the modificationsand variations of the embodiments of the present disclosure fall withinthe scope of the claims of the present disclosure and their equivalenttechnologies, the present disclosure is also intended to include themodifications and variations.

1. A driving method for a shift register, comprising: under a conditionthat at first refreshing frequency, a display frame comprises a datarefreshing phase and a data holding phase, in the data refreshing phase,loading an input signal having a pulse level to an input signal end,loading a control clock pulse signal to a control clock signal end,loading a noise reduction clock pulse signal to a noise reduction clocksignal end, loading a fixed voltage signal having a first level to afirst reference signal end, loading a fixed voltage signal having asecond level to a second reference signal end, controlling a cascadesignal end of the shift register to output a cascade signal having apulse level, and controlling a drive signal end of the shift register tooutput a drive signal having a pulse level; and in the data holdingphase, loading a fixed voltage signal to the input signal end, loading afirst set signal to the control clock signal end, loading a second setsignal to the noise reduction clock signal end, loading the fixedvoltage signal having the first level to the first reference signal end,loading the fixed voltage signal having the second level to the secondreference signal end, controlling the cascade signal end to output thefixed voltage signal having the second level, and controlling the drivesignal end to output the fixed voltage signal having the first level,wherein the control clock pulse signal has the first level, the secondlevel and a first clock period, the first set signal has a first setlevel, wherein the first clock period comprises a duration of one firstlevel and a duration of one second level of the control clock pulsesignal, one of the first level and the second level of the control clockpulse signal is a control clock pulse level, the control clock pulselevel is the same as the first set level, and a maintaining duration ofthe first set level in the first clock period is longer than amaintaining duration of the control clock pulse level in the first clockperiod; and/or, the noise reduction clock pulse signal has the firstlevel, the second level and a second clock period, the second set signalhas a second set level, wherein the second clock period comprises aduration of one first level and a duration of one second level of thenoise reduction clock pulse signal, one of the first level and thesecond level of the noise reduction clock pulse signal is a noisereduction clock pulse level, the noise reduction clock pulse level isthe same as the second set level, and a maintaining duration of thesecond set level in the second clock period is longer than a maintainingduration of the noise reduction clock pulse level in the second clockperiod.
 2. The driving method according to claim 1, wherein the firstset signal is a clock pulse signal, and the first set level is one ofthe first level and the second level.
 3. The driving method according toclaim 2, wherein a third clock period of the first set signal is longerthan the first clock period, wherein the third clock period comprises aduration of one first level and a duration of one second level of thefirst set signal.
 4. The driving method according to claim 2, wherein amaintaining duration of the first level of the first set signal in thefirst clock period is longer than a maintaining duration of the firstlevel of the control clock pulse signal in the first clock period; and amaintaining duration of the second level of the first set signal in thefirst clock period is longer than a maintaining duration of the secondlevel of the control clock pulse signal in the first clock period. 5.The driving method according to claim 1, wherein the second set signalis a clock pulse signal, and the second set level is one of the firstlevel and the second level.
 6. The driving method according to claim 5,wherein a fourth clock period of the second set signal is longer thanthe second clock period, and the fourth clock period comprises aduration of one first level and a duration of one second level of thesecond set signal.
 7. The driving method according to claim 5, wherein amaintaining duration of the first level of the second set signal in thesecond clock period is longer than a maintaining duration of the firstlevel of the noise reduction clock pulse signal in the second clockperiod; and a maintaining duration of the second level of the second setsignal in the second clock period is longer than a maintaining durationof the second level of the noise reduction clock pulse signal in thesecond clock period.
 8. The driving method according to claim 6, whereina third clock period of the first set signal is the same as the fourthclock period of the second set signal.
 9. The driving method accordingto claim 1, wherein at least one of the first set signal and the secondset signal is a fixed voltage signal; and at least one of the first setlevel and the second set level is one of the first level and the secondlevel.
 10. The driving method according to claim 1, wherein the firstlevel is a high level, and the second level is a low level; or, thefirst level is a low level, and the second level is a high level. 11.The driving method according to claim 1, further comprising: under acondition that at second refreshing frequency, a display frame comprisesthe data refreshing phase, in the data refreshing phase, loading theinput signal having the pulse level to the input signal end, loading thecontrol clock pulse signal to the control clock signal end, loading thenoise reduction clock pulse signal to the noise reduction clock signalend, loading the fixed voltage signal having the first level to thefirst reference signal end, loading the fixed voltage signal having thesecond level to the second reference signal end, controlling the cascadesignal end of the shift register to output the cascade signal having thepulse level, and controlling the drive signal end of the shift registerto output the drive signal having the pulse level.
 12. A driving circuitfor a shift register, wherein at first refreshing frequency, a displayframe comprises a data refreshing phase and a data holding phase; andthe driving circuit is configured to: in the data refreshing phase, loadan input signal having a pulse level to an input signal end, load acontrol clock pulse signal to a control clock signal end, load a noisereduction clock pulse signal to a noise reduction clock signal end, loada fixed voltage signal having a first level to a first reference signalend, load a fixed voltage signal having a second level to a secondreference signal end, control a cascade signal end of the shift registerto output a cascade signal having a pulse level, and control a drivesignal end of the shift register to output a drive signal having a pulselevel; and in the data holding phase, load a fixed voltage signal to theinput signal end, load a first set signal to the control clock signalend, load a second set signal to the noise reduction clock signal end,load the fixed voltage signal having the first level to the firstreference signal end, load the fixed voltage signal having the secondlevel to the second reference signal end, control the cascade signal endto output the fixed voltage signal having the second level, and controlthe drive signal end to output the fixed voltage signal having the firstlevel, wherein the control clock pulse signal has the first level, thesecond level and a first clock period, the first set signal has a firstset level, wherein the first clock period comprises a duration of onefirst level and a duration of one second level of the control clockpulse signal, one of the first level and the second level of the controlclock pulse signal is a control clock pulse level, the control clockpulse level is the same as the first set level, and a maintainingduration of the first set level in the first clock period is longer thana maintaining duration of the control clock pulse level in the firstclock period; and/or, the noise reduction clock pulse signal has thefirst level, the second level and a second clock period, the second setsignal has a second set level, wherein the second clock period comprisesa duration of one first level and a duration of one second level of thenoise reduction clock pulse signal, one of the first level and thesecond level of the noise reduction clock pulse signal is a noisereduction clock pulse level, the noise reduction clock pulse level isthe same as the second set level, and a maintaining duration of thesecond set level in the second clock period is longer than a maintainingduration of the noise reduction clock pulse level in the second clockperiod.
 13. The driving circuit according to claim 12, wherein at secondrefreshing frequency, a display frame comprises the data refreshingphase; and the driving circuit is further configured to: in the datarefreshing phase, load the input signal having the pulse level to theinput signal end, load the control clock pulse signal to the controlclock signal end, load the noise reduction clock pulse signal to thenoise reduction clock signal end, load the fixed voltage signal havingthe first level to the first reference signal end, load the fixedvoltage signal having the second level to the second reference signalend, control the cascade signal end of the shift register to output thecascade signal having the pulse level, and control the drive signal endof the shift register to output the drive signal having the pulse level.14. A display panel, comprising a gate drive circuit and the drivingcircuit according to claim 12, wherein the gate drive circuit comprisesa plurality of shift registers cascaded; and the driving circuit iselectrically connected to the plurality of shift registers.
 15. Adisplay device, comprising the display panel according to claim
 14. 16.The driving method according to claim 3, wherein a maintaining durationof the first level of the first set signal in the first clock period islonger than a maintaining duration of the first level of the controlclock pulse signal in the first clock period; and a maintaining durationof the second level of the first set signal in the first clock period islonger than a maintaining duration of the second level of the controlclock pulse signal in the first clock period.
 17. The driving methodaccording to claim 6, wherein a maintaining duration of the first levelof the second set signal in the second clock period is longer than amaintaining duration of the first level of the noise reduction clockpulse signal in the second clock period; and a maintaining duration ofthe second level of the second set signal in the second clock period islonger than a maintaining duration of the second level of the noisereduction clock pulse signal in the second clock period.
 18. The drivingmethod according to claim 7, wherein a third clock period of the firstset signal is the same as the fourth clock period of the second setsignal.